Content-addressable memory (CAM) cells are frequently used. CAM cells perform RAM functions (writing and storing data), but also test or compare the stored data to determine if the data matches test data applied to the memory. When the newly-applied test data matches the data already stored in the memory, a match line is activated, indicating that the stored data matches the test data. CAMs are especially useful for fully-associative memories such as look-up tables and memory-management units.
Each CAM cell is essentially a RAM cell with a match function. Match functions can be implemented by adding an exclusive-OR (XOR) or inverse XOR gate to each RAM cell. The XOR output is applied to a match line that connects many CAM cells together in a row or column. The match signal can then be output from the memory.
CAM cells were originally constructed from static RAM (SRAM) cells by adding transistors to perform the XOR function. More recently, CAM cells have also been constructed from dynamic RAM (DRAM) cells. DRAM cells have an area and cost advantage over SRAM cells since a small capacitor stores charge rather than a bi-stable or cross-coupled pair of transistors.
Dynamic Cam Cells--FIG. 1
FIG. 1 shows a prior-art dynamic CAM cell using six transistors. U.S. Pat. No. 5,428,564 by Winters shows a six-transistor (6T) CAM cell based on earlier dynamic CAM cells of just 4 or 5 transistors. While the earlier 4T and 5T CAM cells were small in area, these cells were particularly noise sensitive and slow, having relatively low voltage ratios.
Winter's CAM cell is written by raising the voltage on the write line, which activates pass transistors 12, 14. True and complement data are applied to bit lines BL and BLB, which are passed through pass transistors 12, 14 to store charge on the gates of storage transistors 18, 16. The sources of storage transistors 16, 18 are also connected to bit lines BL, BLB so that an additional voltage difference from gate to source is created, increasing the stored charge. For example, when BL is high and BLB is low, the high voltage from BL is transmitted to the gate of storage transistor 18, while the low voltage from BLB is applied to the source of storage transistor 18. At the same time, the low voltage from BLB is transmitted to the gate of storage transistor 16, while the high voltage from BLB is applied to the source of storage transistor 16. Thus storage transistors 16, 18 are charge oppositely during a write. Inverse read signal RD-NOT is high during write, and diode transistor 10 stays off so that the drains of storage transistors 16, 18 do not discharge the bit lines.
During a read, signal RD-NOT is low, and diode transistor 10 pulls low the drains of storage transistors 16, 18. One of bit lines BL, BLB is pulled low, depending on which of storage transistors 16, 18 has its gate charged high during the last write. The cell's data can then be read as a voltage difference across the bit lines using a sense amplifier. The CAM cell can be periodically refreshed by reading and then writing back the data to the cell.
During a compare or match operation, match line MATCH and RD-NOT are high and WRITE is low. The bit lines BL and BLB are precharged low. One of the bit lines is then pulled high with the test data. When the test data matches the stored data, storage transistor 16 or 18 connected to the raised bit line is off, preventing the drains from being charged high. The low voltage is applied to the gate of match transistor 20, which does not turn on, keeping MATCH high. When the test data mismatches the stored data, the storage transistor 16 or 18 connected to the raised bit line is turned off, charging high the drains of storage transistors 16, 18. The high drain voltage is applied to the gate of match transistor 20, turning it on, discharging MATCH low.
Winter's CAM cell uses only n-channel (NMOS) transistors, and has a small area. However, bit-line capacitance is high, since the sources of storage transistors 16, 18 are connected directly to the bit lines, as are pass transistors 12, 14. The high bit-line capacitance slows read and write operations. Also, there is the danger of sub-threshold leakage through storage transistors 12, 14 and of disturbance of the storage node from the bit lines. Another disadvantage is the layout efficiency in the MATCH/WL direction. The pitch in this direction may be greater than desired. The gate voltage of transistor 20 can only go as high as VCC-Vt; thus its current drive is weak.
Cmos Dynamic Cam Cell--FIG. 2
FIG. 2 is a prior-art dynamic CAM cell using CMOS transistors. See U.S. Pat. No. 4,791,606 by Threewitt et al. A single bit of data is stored on capacitor 28 when pass transistor 22 is activated by word line WL. Only one bit line BL is used.
An XOR gate is formed by n-channel transistors 24, 28 and p-channel transistors 21, 23. The stored data from capacitor 28 is applied to the gates of transistors 23, 26, while the bit line BL drives the gates of transistors 21, 24. The source of n-channel transistor 26 and the drain of n-channel transistor 23 are driven by mask line MASK, which is pulled low when the CAM cell is being compared. MASK can be pulled high to mask off or disable some cells from being compared. The drain of n-channel transistor 24 and the source of n-channel transistor 21 are connected to match line MATCH.
During a compare or match operation, the inverse data is applied to bit line BL, which is sometimes designated BL/CB to indicate that true data is applied during write, but complement data during compare. Word line WL is kept low so pass transistor 22 is off. Thus the stored data is applied to the gates of transistors 23, 26, while the complement of the test data is applied to the gates of transistors 21, 24 from the bit line. When the stored data and the complement driven to BL do not match, one of transistors 24, 26 in series is on and the other is off. Likewise, one of transistors 21, 23 is on and the other is off. Thus neither series connection has both transistors on, and the match line is not discharged low to MASK, which is driven low during compare. Thus a match is signaled.
When the stored data does match the complement data on BL, the match line is pulled low (a mis-match). If the stored data is high and BL is high, n-channel transistors 24, 26 are both on but p-channel transistors 21, 23 are both off. MATCH is discharged through n-channel transistors 24, 26. For low stored data and BL low, p-channel transistors 21, 23 discharge MATCH.
All-Nmos Cam Cell--FIG. 3
The parent application describes a CAM cell that uses only n-channel transistors. It uses dynamic storage rather than static storage, reducing the size of the CAM cell. A compact layout for the NMOS dynamic CAM cell was also shown.
FIG. 3 is a diagram of a dynamic differential CAM cell with just 6 NMOS transistors as described in the parent application. This CAM cell stores one bit of data, but the data is stored differentially as true and complement data.
A pair of bit lines BL, BLB carry true and complement data to a column of cells. Pass transistors 32, 42 are turned on when word line WL is driven with a high voltage during a write operation. Pass transistors 32, 42 connect bit lines BL, BLB to the gates of storage transistors 36, 46. One gate is charged high while the other gate is charged low. For a data 1, bit line BL is high, storing a high voltage on the gate of storage transistor 36. Bit line BLB is low, driving a low voltage on the gate of storage transistor 46. When word line WL is driven low, storage transistor 36 stores a positive charge while storage transistor 46 stores little or no charge. The opposite occurs when a data 0 is written to the cell.
Match line MATCH is held low during reads and writes so that storage transistors 34, 44 act as capacitors to ground. The sources of storage transistors 36, 46 are connected to ground. A virtual or switched ground such as a MASK line can be substituted. MATCH is precharged high before a compare operation.
The cell can be read by equalizing and precharging both bit lines BL, BLB to an intermediate voltage before word line WL is raised. One bit line is then driven low and the other is driven high by charge sharing as pass transistors 32, 42 are turned on. A sensitive sense amplifier can then detect a slight voltage difference on bit lines BL, BLB. The cell can be refreshed by writing the sensed data back to the bit lines.
N-channel transistors 34, 36, 44, 46 perform an XOR function since true and complement data are stored on the gates of storage transistors 36, 46. During a match or compare operation, word line WL is low and pass transistors 32, 42 remain off. Thus the stored charge on the gates of storage transistors 34, 44 is isolated and not disturbed.
The test data from bit lines BL, BLB are applied to the gates of match transistors 34, 44, respectively. The complements of the test data are applied to these bit lines during the compare operation. Thus bit line BL carries the complement of the test data, and can be designated BL/CB, where CB refers to the inverse compare data or compare-bar. Complement bit line BLB carries the true test data, and can be designated BLB/C.
The stored data or stored charge on the gate of storage transistor 36 turns this transistor on when high but off when the data (charge) is low. When the test data is low (a mis-match), the test-data complement CB is high, and thus a high signal is applied to bit line BL/CB. Both transistors 34, 36 are turned on, causing match line MATCH to be discharged to ground. Thus a mis-match is signaled.
MATCH is also pulled low when the stored data is high but the test data is low. The low stored data causes the gate of storage transistor 36 to be low, keeping it off. However, the gate of storage transistor 46 is charged high, turning it on. Bit line BLB receives the true test data (high), which is applied to the gate of transistor 44, turning it on. Since both transistors 44, 46 are turned on, the MATCH line is discharged through these series-connected transistors. A mis-match is signaled.
When the test data matches the stored data in the CAM cell, match line MATCH remains high. For example, when the cell stores a 1, storage transistor 36 is on but storage transistor 46 is off. The true test data is applied to bit line BLB while the complement test data is applied to bit line BL. Since the test data is also a 1, BL is low while BLB is high. Thus transistor 34 is off, blocking current flow through storage transistor 36. Thus no discharge path to ground occurs, since transistors 34, 46 are off.
The opposite occurs when the cell stores a 0, which is compared to a 0 test data.
The CAM cell requires only 6 transistors. Since all 6 transistors are NMOS, the cell does not have to expand for well-to-well spacing as only a P-well or p-substrate is present within the cell. Of course, a full CMOS process may be used for the periphery circuits.
FIG. 4 is another alternate embodiment described in the parent application with write-enable transistors. Write-enable transistors 31, 41 are added in series with pass transistors 32, 42. The cell can be written but not read. Some applications such as imaging do not require reading since the data is not stored for more than the refresh period. Instead, the data is quickly used (compared but not read) and discarded.
While the parent application's CAM cell is area-efficient, using only n-channel transistors, a full voltage swing on the word or row lines is needed to access the cell. Word-line drivers using charge pumps could be used to elevate the word-line voltage above the power-supply voltage, but these pump circuits are complex. It is desired to modify the CAM cell described in the parent application to increase the voltage on the gate of the pass transistors, without using a charge pump. Using locally-pumped nodes for pass transistors allows for higher voltage-drive without external charge pumps. Smaller device sizes can be used for the pass transistors while still allowing sufficient current to flow when charging or discharging the dynamic nodes of the CAM cell.
What is desired is a CAM cell with locally-pumped pass-transistor gates. It is desired to use only n-channel transistors. It is desired to use dynamic storage rather than static storage to reduce the size of the CAM cell. A dynamic CAM cell is desired that pumps the pass-transistor gate voltage above the power-supply voltage without using a word-line charge pump. A compact layout for an NMOS dynamic CAM cell is also desired.